FIG. 25 is a sectional view illustrating a prior art infrared detector. In the figure, the infrared detector 551 includes a p type CdTe substrate 1 having opposite front and rear surfaces. A p type Cd.sub.0.2 Hg.sub.0.8 Te layer 2 is disposed on the front surface of the p type CdTe substrate 1. N type CdHgTe regions 31 and 32 are disposed within the p type Cd.sub.0.2 Hg.sub.0.8 Te layer 2, reaching the surface, and negative electrodes 61 and 62 are disposed in contact with the CdHgTe regions 31 and 32, respectively. A positive electrode 5 is disposed on the rear surface of the p type CdTe substrate 1. Reference numerals 41 and 42 designate pn junctions. Reference numerals 101 and 102 designate infrared light responsive parts serving as pixels. Reference numeral 70 designates infrared light having a wavelength of 10 .mu.m. Reference numerals 71 and 72 designate electrons. Although only two pixels 101 and 102 are shown in the FIG. 25, the infrared detector 551 includes a lot of pixels.
A description is given of the operation. The infrared light 70 incident on the CdTe substrate 1 is transmitted through the CdTe substrate 1 and absorbed in the p type Cd.sub.0.2 Hg.sub.0.8 Te layer 2, producing electron-hole pairs. When electrons 71 and 72, i.e., minority carriers, reach the pn junctions 41 and 42, electric power representative of the quantity of the infrared light is output through the negative electrodes 61 and 62. In this way, the incidence of infrared light on each light responsive part, i.e., each pixel, can be detected by output power from each going power output. Therefore, this infrared detector 551 including a lot of pixels outputs electric signals representing an infrared image.
In this prior art infrared detector, however, a electron 71 that is produced in response to infrared light incident on a part of the substrate 1 opposite the pixel 101 unfavorably diffuses toward the pixel 102 and reaches the pn junction 42 of the pixel 102. Likewise, an electron 72 produced opposite the pixel 102 reaches the pn junction 41 of the pixel 101. In this case, the incident position of the infrared light is misjudged, i.e., crosstalk occurs.
Generally, the diffusion length of electrons in the p type Cd.sub.0.2 Hg.sub.0.8 Te layer is about 40 .mu.m. If the space between adjacent pixels is less than this diffusion length, the above-described crosstalk occurs, reducing the resolution. Therefore, an infrared detector with high resolution and high integration density cannot be realized.
FIG. 26 illustrates a sectional view of a prior art infrared detector that prevents the above-described problems, disclosed in Japanese Published Patent Application No. Hei. 2-272766. In FIG. 26 an infrared detector 552 includes a p type Cd.sub.0.3 Hg.sub.0.7 Te substrate 14 having opposite front and rear surfaces. P type Cd.sub.0.2 Hg.sub.0.8 Te layers 21 and 22 are disposed within the p type Cd.sub.0.3 Hg.sub.0.7 Te substrate 14, reaching the front surface. N type CdHgTe regions 31 and 32 are disposed within the p type Cd.sub.0.2 Hg.sub.0.8 Te layers 21 and 22, respectively, and negative electrodes 61 and 62 are disposed on the front surface of the substrate 14, contacting the n type CdHgTe regions 31 and 32, respectively. Positive electrodes 51 are disposed on the front surface of the substrate 14, contacting the p type Cd.sub.0.2 Hg.sub.0.8 Te layers 21 and 22, respectively. Reference numerals 42 and 43 designate pn junctions. Reference numerals 101 and 102 designate infrared light responsive parts, i.e., pixels, of the infrared detector. MIS-FET (Metal Insulator Silicon Field Effect Transistor) switching elements 111 and 112 are disposed in the vicinity of the respective pixels 101 and 102 at the front surface of the substrate 14. Each MIS-FET switching element includes source and drain diodes 81 and 82, source and drain electrodes 83 and 84, and a gate electrode 85. These MIS-FET switching elements 111 and 112 are connected to the positive electrodes 51 of the pixels 101 and 102, respectively, via wiring layers 86.
A description is given of the operation. Infrared light 70 having a wavelength of 10 .mu.m is incident on the rear surface of the p type Cd.sub.0.3 Hg.sub.0.7 Te substrate 14 and absorbed in the p type Cd.sub.0.2 Hg.sub.0.8 Te layers 21 and 22, whereby electric power representative of the quantity of the infrared light is produced. The electric power is output from the detector 552 according to the switching operation of the MIS-FETs 111 and 112.
In this prior art infrared detector, since the respective pixels are separated from each other by the substrate 14, the unwanted diffusion of charge carriers between adjacent pixels is prevented.
In production of this prior art infrared detector, a plurality of recesses are formed at the front surface of the Cd.sub.0.3 Hg.sub.0.7 Te substrate 1 and, thereafter, the light responsive Cd.sub.0.2 Hg.sub.0.8 Te layers are deposited in these recesses. In order to adequately absorb the incident infrared light, the depth of the recess must be at least 10 .mu.m. However, it is very difficult to produce such recesses in the Cd.sub.0.3 Hg.sub.0.7 Te substrate at high density.
Further, since the MIS-FET switching elements are disposed between the respective pixels, the space between the adjacent pixels must be about 10 .mu.m and, therefore, high-density integration is not realized.